SavedAdd your journal

Journals / International Advanced Researches and Engineering Journal / 2018 / Cilt: 2 - Sayı: 3

Design and implementation of the FPGA-based chaotic van der pol oscillator

Mustafa DURSUN
Elif KAŞİFOĞLU
Pages
309–314
Publication Date
2022-10-19
DOI
—
🏛️Bibliographic metadata and full text access for this article are provided via DergiPark.
DergiPark Record ↗
✨

AI Summary & Key Takeaways

AI Insight
⚡ TL;DR(Too Long; Didn't Read)

Additionally, chip statistics of the FPGA-based Van der Pol oscillator were presented.

📌 3 Key Takeaways

🎯
Objective & Hypothesis:In this study, the chaotic Van der Pol system was implemented for real-time chaos applications on FPGA chip.
📊
Key Findings & Data:The chaotic Van der Pol system was coded in Very High-Speed Integrated Circuits Hardware Description Language (VHDL) with 32-bit IEEE-754-1985 floating point number standard.
💡
Conclusion & Impact:Additionally, chip statistics of the FPGA-based Van der Pol oscillator were presented.
🔬Design:Modeling & Simulation
📍Scope:Comprehensive Sample
⚙️Variables:FPGA Chips · Van Der Pol Oscillator · VHDL

Abstract

In this study, the chaotic Van der Pol system was implemented for real-time chaos applications on FPGA chip. The chaotic Van der Pol system was also modelled numerically by using the Euler algorithm ODE (Ordinary Differential Equation) solver on Matlab. Numerical structure of the chaotic Van der Pol oscillator designed on Matlab was taken as reference for the design of FPGA-based chaotic Van der Pol oscillator unit. The chaotic Van der Pol system was coded in Very High-Speed Integrated Circuits Hardware Description Language (VHDL) with 32-bit IEEE-754-1985 floating point number standard. The designed chaotic Van der Pol system was synthesized in the Xilinx ISE Project Navigator program and was implemented on the Xilinx VIRTEX-6 chip family, XC6VLX75T device, FF784 package. The maximum operating frequency of the FPGA-based chaotic Van der Pol oscillator unit obtained from Place and Route processes was 498.728 MHz. Additionally, chip statistics of the FPGA-based Van der Pol oscillator were presented.

🔖

Cite This Article

DURSUN, M., KAŞİFOĞLU, E. (2022). Design and implementation of the FPGA-based chaotic van der pol oscillator. International Advanced Researches and Engineering Journal, Cilt: 2 - Sayı: 3, 309–314. https://ajindex.com/articles/539414

📄 Full Text PDF Viewer

📄

PDF görüntüleyici hazırlanıyor...

References (12)

  1. Tuna, M., Fidan, C.B., Electronic circuit design, implementation and FPGA-based realization of a new 3D chaotic system with single equilibrium point. Optik-International Journal for Light and Electron Optics, 2016. 127(24): p. 11786-11799
  2. Belkhouja, T., Mohamed, A., Al-Ali, A.K., Du, X., Guizani, M., Light-weight encryption of wireless communication for implantable medical devices using henon chaotic system. In Wireless Networks and Mobile Communications (WINCOM), IEEE 2017 International Conference on. p. 1-6
  3. Wang, X., Akgul, A., Cicek, S., Pham, V. T., & Hoang, D. V., A chaotic system with two stable equilibrium points: Dynamics, circuit realization and communication application. International Journal of Bifurcation and Chaos, 2017. 27(08): p. 1750130
  4. Ji Y, Zhang M, Wang Y, Wang P, Wang A, Wu Y, et al., Microwave-Photonic Sensor for Remote Water-Level Monitoring Based on Chaotic Laser. International Journal of Bifurcation and Chaos, 2014. 24: 1450032
  5. Ashita S, Uma G, Deivasundari P. Chaotic dynamics of a zero average dynamics controlled DC–DC Ćuk converter. IET Power Electronics, 2014. 7: p. 289–98
  6. Pomares J., Perea I., Torres F., Dynamic Visual Servoing With Chaos Control for Redundant Robots. IEEE/ASME Transactions on Mechatronics, 2014. 19: p. 423–31
  7. Alçın, M., The Modelling Performance Evolution of Recurrent Neural Networks Having Different Training Functions for Modelling Sprott H Chaotic System. Int. Journal on Research Innovations in Engineering Science and Technology, 2017. 2(10): p. 563–568
  8. Alçın M, Pehlivan İ, Koyuncu İ, Hardware design and implementation of a novel ANN-based chaotic generator in FPGA. Elsevier, Optik-International Journal for Light and Electron Optics, 2016. 127(13): p. 5500-5505
  9. Koyuncu İ, Şahin İ, Gloster C, Sarıtekin N.K., A Neuron Library for Rapid Realization of Artificial Neural Networks on FPGA: A Case Study of Rössler Chaotic System. Journal of Circuits, Systems and Computers, 2017. 26(01): p. 1750015
  10. Avaroğlu, E., Pseudorandom number generator based on Arnold cat map and statistical analysis. Turkish Journal of Electrical Engineering & Computer Sciences, 2017. 25(1): p. 633-643
  11. Fidan, C. B., Tuna M., A Study on the importance of chaotic oscillators based on FPGA for true random number generating (TRNG) and chaotic systems. Journal of the Faculty of Engineering and Architecture of Gazi University, 2018. 33(2): p. 469-486
  12. Shi, K., Tang, Y., Liu, X., & Zhong, S., Non-fragi