AI Summary & Key Takeaways
AI InsightAccording to the results, the maximum operating frequency of DP-based SPCO unit on FPGA is obtained as 362.608 MHz.
📌 3 Key Takeaways
Abstract
Chaos is one of the important research areas in recent years. The chaotic signal generator is one of the most basic structure in the chaos-based researches and applications. In this study, Sundarapandian-Pehlivan Chaotic Oscillator (SPCO) designs have been implemented in 2 different platforms as analog-based using Second-Generation Current Controlled Current Conveyor (CCII) and FPGA-based with one of the chaotic oscillator that has been presented to the literature namely Sundarapandian-Pehlivan system. The structure used for the design of CCII-based chaotic oscillator and the results obtained from the study have been presented. In the second phase, the design of SPCO has been realized in order to utilize for running in FPGA chips using Dormand-Prince (DP) numeric algorithm. The design has been coded in VHDL using 32-bit IEEE-754-1985 floating point representation. The designed system has been tested by synthesizing it in Xilinx ISE Design Tools program. Then, the test results obtained from DP-based SPCO structure have been presented. In the last phase, the designed system has been synthesized for VIRTEX-7 FPGA. FPGA chip resource consumption values that obtained after the Place-Route process are presented. According to the results, the maximum operating frequency of DP-based SPCO unit on FPGA is obtained as 362.608 MHz. In future studies, the designs of Pseudo Random Number Generator (RNG) and True RNG can be performed using DP-based SPCO unit implemented successfully in this study.