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Yapay Zeka Hızlı Bakış & Çıkarımlar
AI Insight⚡ TL;DR(1 Cümlede Hızlı Çıkarım)
By a VHDL simulator, the adder structures are simulated to verify the functional correctness and to measure delay times
📌 3 Maddede Bu Makale
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Amaç & Hipotez:In this paper, the four binary adder architectures belong to a different adder class are studied and compared with each other to analyse their performances.
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Temel Bulgular & Veri:As the performance measure, the product of the area and the delay is used.
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Sonuç & Katkı:By a VHDL simulator, the adder structures are simulated to verify the functional correctness and to measure delay times
🔬Tür:Modelleme & Sayısal Simülasyon
📍Kapsam:Genişletilmiş Akademik Örneklem
⚙️Değişkenler:Alan Parametreleri
Abstract
In this paper, the four binary adder architectures belong to a different adder class are studied and compared with each other to analyse their performances. Comparisons include the unit-gate models for area and delay. As the performance measure, the product of the area and the delay is used. By a VHDL simulator, the adder structures are simulated to verify the functional correctness and to measure delay times
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Bu Makaleye Atıf Yap
SERTBAŞ, A., ÖZBEY, R. S. (2022). A performance analysis of classified binary adder architectures and the VHDL simulations. Istanbul University Journal of Electrical and Electronics Engineering, Cilt: 4 - Sayı: 1, 1025–1030. https://ajindex.com/articles/543877