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Dergiler / Istanbul University Journal of Electrical and Electronics Engineering / 2004 / Cilt: 4 - Sayı: 1

Complementary pass transistor logic synthesis with 123 decision diagram

Tülay YILDIRIM
Mutlu AVCI
Sayfa
1045–1049
Yayın Tarihi
2022-10-18
DOI
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⚡ TL;DR(1 Cümlede Hızlı Çıkarım)

Cell circuits for the 4 bit adder is realized with the CMOS pass transistors using the 123 decision diagram and 4 bit adder is completed by combining the cells.

📌 3 Maddede Bu Makale

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Amaç & Hipotez:123 decision diagram is a very effective PTL synthesis tool based on binary decision diagram.
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Temel Bulgular & Veri:In this paper the 123 decision diagram is applied to realize CMOS pass transistor logic circuits without restoring buffers.
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Sonuç & Katkı:Cell circuits for the 4 bit adder is realized with the CMOS pass transistors using the 123 decision diagram and 4 bit adder is completed by combining the cells.
🔬Tür:Araştırma Makalesi
📍Kapsam:Genişletilmiş Akademik Örneklem
⚙️Değişkenler:Alan Parametreleri

Abstract

123 decision diagram is a very effective PTL synthesis tool based on binary decision diagram. It realizes a logic function using NMOS pass transistors with CMOS restoring buffers. In this paper the 123 decision diagram is applied to realize CMOS pass transistor logic circuits without restoring buffers. Cell circuits for the 4 bit adder is realized with the CMOS pass transistors using the 123 decision diagram and 4 bit adder is completed by combining the cells.

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Bu Makaleye Atıf Yap

YILDIRIM, T., AVCI, M. (2022). Complementary pass transistor logic synthesis with 123 decision diagram. Istanbul University Journal of Electrical and Electronics Engineering, Cilt: 4 - Sayı: 1, 1045–1049. https://ajindex.com/articles/543867

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Kaynakça (7)

  1. Jeakel A., Bandyopadyah S., and Jullien G. A., "Design of Dynamic Pass-Transistor Logic Circuits Using 123 Decision Diagrams”, IEEE Trans. on Circuits and Systems-I, vol. 45, no. 11, pp. 1172-1181, November 1998
  2. Markovic D., Nikolic B., and Oklobdzija V. G., "A General Method in Synthesis of Pass-Transistor Circuits”, Microelectronics Journal, vol. 31, pp. 991-998, 2000
  3. Abadir M. S., Reghabati H. K., “Fuctional Test Generation For Digital Circuits Described Using Binary Decision Diagram”. IEEE Trans. on Comput., Vol C-35, pp 375-379, April 1986
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  5. Cheung T. S., Asada K., “Regenerative Pass Transistor Logic: A Circuit Technique For High Speed Digital Design”, IEICE Transact. on Electronics, Vol E-79C, Iss 9, pp 1274-1284, September 1996
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  7. Yano K., Sasaki Y., Rikino K., Seki K., “Top Down Pass Transistor Logic Design”, IEEE Jour. of Solid State Circuits, Vol 31, Iss 6, pp 792-803, 1996.