The proposed design uses approximately 10% more hardware and has 33% more delay compared to a conventional double precision floatingpoint multiplier.
📌 3 Maddede Bu Makale
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Amaç & Hipotez:Modern graphic processors, multimedia processors, and general-purpose processors with multimedia extensions provide SIMD floating-point instructions.
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Temel Bulgular & Veri:SIMD floating-point multiplication is commonly used in 2D and 3D applications, which mostly use single precision floating-point operands.
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Sonuç & Katkı:The proposed design uses approximately 10% more hardware and has 33% more delay compared to a conventional double precision floatingpoint multiplier.
🔬Tür:Araştırma Makalesi
📍Kapsam:Genişletilmiş Akademik Örneklem
⚙️Değişkenler:Alan Parametreleri
Abstract
Modern graphic processors, multimedia processors, and general-purpose processors with multimedia extensions provide SIMD floating-point instructions. SIMD floating-point multiplication is commonly used in 2D and 3D applications, which mostly use single precision floating-point operands. Consequently, efficient single precision multiplier units are crucial for high performance systems. This paper introduces a novel floating point multiplier that can perform either a double precision or two parallel single-precision floating-point multiplications. The proposed design uses approximately 10% more hardware and has 33% more delay compared to a conventional double precision floatingpoint multiplier.
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Bu Makaleye Atıf Yap
GÖK, M., ÖZBİLEN, M. M. (2022). A single/double precision floating-point multiplier design for multimedia applications. Istanbul University Journal of Electrical and Electronics Engineering, Cilt: 9 - Sayı: 1, 827–831. https://ajindex.com/articles/543759
V. Lappalainen, T.D. Hämäläinen, P. Liuha, “Overview of Research Efforts on Media ISA Extensions and Their Usage in Video Coding”, IEEE Transactions on Circuits And Systems For Video Technology, Vol: 12, No: 8, 2002
G. Even, S.M. Mueller, P.M. Seidel, “A dual mode IEEE multiplier Proceedings”, Second Annual IEEE International Conference, pp. 282- 289, 1997
R.B. Lee, “Multimedia extensions for general purpose processors, Signal Processing Systems, 1997”, SIPS 97 - Design and Implementation., IEEE Workshop, pp. 9-23, 1997
ANSI-IEEE Standard 754-1985: “IEEE Standard for binary floating-point arithmetic”, 1985
K. Diefendorff, P.K. Dubey, R. Hochsprung, H. Scale, “AltiVec extension to PowerPC accelerates media processing”, IEEE Micro, Vol: 20 Iss: 2, pp. 85-95, 2000
M.D. Jennings, T.M. Conte, “Subword Extensions for Video Processing on Mobile Systems”, IEEE Concurrency, Vol: 6, No: 3, pp. 13-16, 1998
M. Gök, S. Krithivasan, M.J. Schulte, “Designs for Subword-Parallel Multiplications and Dot Product Operations”, Workshop on Application Specific Processors, pp. 27-31, 2004.