SavedAdd your journal

Journals / Mühendislik Bilimleri ve Araştırmaları Dergisi / 2023 / Cilt: 5 Sayı: 1

A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM

Halit ÖZTEKİN
İhsan PEHLİVAN
Abdelkader LAZZEM
Pages
47–56
Publication Date
2023-04-30
DOI
—
🏛️Bibliographic metadata and full text access for this article are provided via DergiPark.
DergiPark Record ↗
✨

AI Summary & Key Takeaways

AI Insight
⚡ TL;DR(Too Long; Didn't Read)

The results indicate that the Flip-flops approach is worse in terms of search speed and resource utilization compared to the other approach.

📌 3 Key Takeaways

🎯
Objective & Hypothesis:his work gives a comparison between two approaches used for improving search operation speed by using FPGA-based Binary Content Addressable Memory (BiCAM), which is a parallel type of computer memory that quickly searches for and retrieves specific data stored within the memory by assigning a unique address to each piece of data.
📊
Key Findings & Data:The performance of these implementations is evaluated through Time complexity analysis, resource utilization, and search speed.
💡
Conclusion & Impact:The results indicate that the Flip-flops approach is worse in terms of search speed and resource utilization compared to the other approach.
🔬Design:Research Article
📍Scope:Comprehensive Sample
⚙️Variables:Field-programmable Gate Array (FPGA) · Search Operation · Binary Content Addressable Memory (BiCAM)

Abstract

his work gives a comparison between two approaches used for improving search operation speed by using FPGA-based Binary Content Addressable Memory (BiCAM), which is a parallel type of computer memory that quickly searches for and retrieves specific data stored within the memory by assigning a unique address to each piece of data. This hardware-based technique is more efficient than traditional software-based techniques such as Linear, Binary, and hash-based. The FPGA-based BiCAM is implemented using two different approaches: using Flip-flops and Block Random Access Memory as the memory element. The performance of these implementations is evaluated through Time complexity analysis, resource utilization, and search speed. The results indicate that the Flip-flops approach is worse in terms of search speed and resource utilization compared to the other approach. With the current increasing demand for faster and more efficient search operations, this approach can play an important role in optimizing search operations.

Özet

This work gives a comparison between two approaches used for improving search operation speed by using FPGA-based Binary Content Addressable Memory (BiCAM), which is a parallel type of computer memory that quickly searches for and retrieves specific data stored within the memory by assigning a unique address to each piece of data. This hardware-based technique is more efficient than traditional software-based techniques such as Linear, Binary, and hash-based. The FPGA-based BiCAM is implemented using two different approaches: using Flip-flops and Block Random Access Memory as the memory element. The performance of these implementations is evaluated through Time complexity analysis, resource utilization, and search speed. The results indicate that the Flip-flops approach is worse in terms of search speed and resource utilization compared to the other approach. With the current increasing demand for faster and more efficient search operations, this approach can play an important role in optimizing search operations.

🔖

Cite This Article

ÖZTEKİN, H., PEHLİVAN, İ., LAZZEM, A. (2023). A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM. Mühendislik Bilimleri ve Araştırmaları Dergisi, Cilt: 5 Sayı: 1, 47–56. https://ajindex.com/articles/911600

📄 Full Text PDF Viewer

📄

PDF görüntüleyici hazırlanıyor...

References (8)

  1. R.Schlesinger, “Developing Real World Software”, Jones & Bartlett Publishers, 2009.
  2. H. Öztekin, F.Temurtas, and A.Gulbag, “BZK.SAU. FPGA10.1: A modular approach to FPGA-based microcomputer architecture design for educational purposes”, Computer Applications in Engineering Education, vol.22, no.2, pp.272–282, 2014.
  3. R. Karam, R. Puri, S. Ghosh and S. Bhunia, "Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories," in Proceedings of the IEEE, vol. 103, no. 8, pp. 1311-1330, Aug. 2015, H. Öztekin, “BiCAM-based automated scoring system for digital logic circuit diagrams”. Open Chemistry, Vol.20, No.1, pp. 1548-1556. Dec.2022
  4. S. Hirasawa, H. Yamaki and M. Koibuchi, "Packet Forwarding Cache of Commodity Switches for Parallel Computers," 2021 IEEE International Conference on Cluster Computing (CLUSTER), pp. 366-376, Sep.2021, D. Jothi, and R. Sivakumar, “Design and Analysis of Power Efficient Binary Content Addressable Memory (PEBCAM) Core Cells”, Circuits, Systems, and Signal Processing, vol.37, no.6, pp.1422–1451, 2018. M. V. Zackriya, and H. M. Kittur, “ Precharge-Free Low-Power Content-Addressable Memory”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, no.8, pp.2614-2621, 2016.
  5. M. Irfan, A.I. Sanka, Z.Ullah, and R.C.C. Cheung, “Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey”, Future Generation Computer Systems, vol.128, pp.451-465, 2021.
  6. Z. Ullah, K.Ilgon, and S. Baeg, “ Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.59, pp.2969-2979, 2012.
  7. A. Ahmed, K. Park, and S. Baeg, “Resource-Efficient SRAM-Based Ternary Content Addressable Memory ”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.25, pp.1583-1587, 2017. J.G. Nash, “Distributed-Memory-Based FFT Archite -cture and FPGA Implementations”, Electronics, vol.7, no.7, pp.116–145, 2018. Z. Ullah, “LH-CAM: Logic-Based Higher Performan -ce Binary CAM Architecture on FPGA”, IEEE Embedded Systems Letters, vol.9, no.2, pp. 29–32, 2017.
  8. Z. Ullah, K. Ilgon, and S.Baeg, “Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.59, pp.2969-2979, 2012. W. Jiang, “Scalable Ternary Content Addressable Memory implementation using FPGAs”, 9th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, pp.71-82. Oct. 2013.