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Journals / Journal of Science, Technology and Engineering Research / 2020 / Cilt: 1 - Sayı: 2

Investigation on The Performance as An Auto-Zero Comparator of Common Gate Differential Amplifier Based CMOS Inverter Circuit

Ortak Gate Fark Yükselteç Tabanlı CMOS İnverter Devresinin Auto-Zero Karşılaştırıcı Performansının İncelenmesi

Oktay AYTAR
Pages
25–32
Publication Date
2020-12-21
DOI
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AI Summary & Key Takeaways

AI Insight
⚡ TL;DR(Too Long; Didn't Read)

The average power consumption of the proposed structure is 15,4mW under the same conditions.

📌 3 Key Takeaways

🎯
Objective & Hypothesis:In this study, the performance of the common gate difference amplifier cmos inverter circuit as an auto-zero comparator circuit was investigated using 0.18μm CMOS process model in the NCSU Design Kit of the Cadence IC5141 design program.
📊
Key Findings & Data:The performance of the proposed structure was compared with traditional inverter circuit and darlington cmos inverter circuit.
💡
Conclusion & Impact:The average power consumption of the proposed structure is 15,4mW under the same conditions.
🔬Design:Modeling & Simulation
📍Scope:Comprehensive Sample
⚙️Variables:Ortak Gate Fark Yükselteç Tabanlı CMOS İnverter · Darlington CMOS İnverter · Auto-Zero Karşılaştırıcı

Abstract

In this study, the performance of the common gate difference amplifier cmos inverter circuit as an auto-zero comparator circuit was investigated using 0.18μm CMOS process model in the NCSU Design Kit of the Cadence IC5141 design program. The performance of the proposed structure was compared with traditional inverter circuit and darlington cmos inverter circuit. In accordance with the results of DC analysis, the voltage gain of the proposed circuit is 138, 92 V/V and it has more gain than the investigated circuits. According to obtained simulation results, the rising edge and descending edge delay times are observed 0.81ns and 0.99ns while operating with a clock frequency of 5GHz and an input frequency the rising and the descending ramp signal of 50 MHz, respectively. The average power consumption of the proposed structure is 15,4mW under the same conditions.

Özet

Yapılan bu çalışmada, Cadence IC5141 tasarım programı NCSU Design Kit’de 0.18μm CMOS teknoloji kütüphanesi kullanılarak ortak gate fark yükselteçli cmos inverter devresinin auto-zero karşılaştırıcı olarak performansı incelenmiştir. Önerilen bu yapı geleneksel inverter devresi ve darlington cmos inverter yapıları ile karşılaştırılmıştır. Yapılan DC analiz sonucuna göre ortak gate fark yükselteçli inverter devresinin gerilim kazancı 138,92 V/V bulunmuş olup, incelenen yapılardan daha fazla kazanca sahip olduğu görülmüştür. Aynı zamanda karşılaştırıcı yapısının girişine 50MHz frekansında yükselen ve inen bir rampa işareti ve saat frekansı da 5GHz uygulandığında, sırasıyla yükselen kenar gecikme süresi 0.81ns, inen kenar gecikme süresi de 0.99ns elde edilmiştir. Bu yapının aynı şartlar altında ki ortalama güç tüketim değeri de 15,4mW’tır.

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Cite This Article

AYTAR, O. (2020). Investigation on The Performance as An Auto-Zero Comparator of Common Gate Differential Amplifier Based CMOS Inverter Circuit. Journal of Science, Technology and Engineering Research, Cilt: 1 - Sayı: 2, 25–32. https://ajindex.com/articles/778919

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References (1)

  1. . P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Second Edition, Oxford University Press, 2002. [2]. R.J. Baker, CMOS Circuit Design, Layout and Simulaton, Wiley-IEEE press, 2019 [3]. Hesham Omran, “Fast and accurate technique for comparator offset voltage simulation”, Microelectronics Journal, 89, pp. 91–97, 2019. [4]. G. Roubik, Introduction to CMOS OP-AMPs and comparators, J Wiley & Sons, 1999. [5]. G. Ahmed and R. K. Baghel, “Design of 6-bit Flash Analog to Digital Converter Using Variable Switching Voltage CMOS Comparator”, International Journal of VLSI Design & Communication Systems (VLSICS) Vol.5, No.3, pp. 25-35, June 2014. [6]. Y. Susanti, P. K. Chan and V. K. S. Ong, “An Ultra Low-Power Successive Approximation ADC Using an Offset-Biased Auto-Zero Comparator”, IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008, pp. 284-287, 2008. [7]. B. P. Hypolite, W. T. E. and M. I. Adolphe, “A 10GHZ Low-Offset Dynamic Comparator for High-Speed and Lower-Power ADCs”, American Journal of Engineering and Applied Sciences, 12 (2), pp. 156-165, 2019. [8]. L. F. Rahman, M. B. I. Reaz, C. C. Yin, M. Marufuzzaman, and M. A. Rahman, “A High-Speed and Low-Offset Dynamic Latch Comparator”, The Scientific World Journal, vol. 2014, Article ID 258068, 8 pages, 2014. [9]. J. Li, H. Fan, Y. Wu, Q. Feng, D. Li, D. Hu, Y. Cen, and H. Heidari, “Comparator Design in Sensors for Environmental Monitoring”, IOP Conference Series: Earth and Environmental Science, Vol. 151, No. 1, p. 012030, 2018. [10]. A. Ahmed, “High speed data converters”, Institution of Engineering and Technology, 2016. [11]. X. Huang, L. Li, Z. Zhang, L. Chen, J. Yu, “High-speed comparator used for high-speed, highresolution A/D converter”, 2010 International Conference on Anti-Counterfeiting, Security and Identification IEEE, pp. 67-70, July 2010. [12]. S. Zhang, Z. Li, B. Ling, “Design of high-speed and low-power comparator in flash ADC", Procedia Engineering 29, pp. 687-692, 2012. [13]. V. Nagy, V. Stopjaková, “New Current Monitor Using Auto Zero Voltage Comparator for IDD Testing of Mixed-signal Circuits”, IEEE Design and Diagnostics of Electronic Circuits and systems, pp. 234-235, 2006. [14]. Y.C. Hung and B.D. Liu, “A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability”, Analog Integrated Circuits and Signal Processing, 32, pp. 219–230, 2002. [15]. M. J. M. Pelgrom, Analog-to-Digital Conversion, Springer, New York, NY, 2013. [16]. J.P. Uyemura, Circuit design