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Journals / Dicle Üniversitesi Fen Bilimleri Enstitüsü Dergisi / 2021 / Cilt: 10 - Sayı: 2

FPGA Based Implementation of 2D Convolution Processing as a Low-Cost IP Core

2D Konvolüsyonun İşleminin Düşük Maliyetli IP Çekirdek Olarak FPGA Tabanlı Gerçeklenmesi

Mehmet Ali ÇAVUŞLU
Pages
235–245
Publication Date
2021-12-30
DOI
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AI Summary & Key Takeaways

AI Insight
⚡ TL;DR(Too Long; Didn't Read)

The results of the synthesis showed that the two-dimensional convolution IP core developed within the scope of the study was realized FPGA-based with low hardware cost.

📌 3 Key Takeaways

🎯
Objective & Hypothesis:In this study, FPGA-based implementation of two-dimensional convolution process, which is frequently preferred in image processing applications, as a low-cost IP core is explained.
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Key Findings & Data:Synthesis results of the IP core are given by taking Artix 7 100T FPGA of Xilinx as a reference.
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Conclusion & Impact:The results of the synthesis showed that the two-dimensional convolution IP core developed within the scope of the study was realized FPGA-based with low hardware cost.
🔬Design:Research Article
📍Scope:Comprehensive Sample
⚙️Variables:FPGA · Görüntü İşleme · 2D Konvolüsyon

Abstract

In this study, FPGA-based implementation of two-dimensional convolution process, which is frequently preferred in image processing applications, as a low-cost IP core is explained. With the IP core developed within the scope of the study, horizontal/vertical Sobel, horizontal/vertical Prewitt, slide-out, low pass filter, high pass filter, and Gaussian filter operations on the image can be realized easily with the parameter set by the user. The IP core platform is designed independently and can be synthesized in software developed by all FPGA manufacturers. Synthesis results of the IP core are given by taking Artix 7 100T FPGA of Xilinx as a reference. The results of the synthesis showed that the two-dimensional convolution IP core developed within the scope of the study was realized FPGA-based with low hardware cost.

Özet

Bu çalışma kapsamında görüntü işleme uygulamalarında sıklıkla tercih edilen iki boyutlu konvolüsyon işleminin düşük maliyetli IP çekirdek olarak FPGA tabanlı gerçeklenmesi anlatılmıştır. Çalışma kapsamında geliştirilen IP çekirdek ile görüntü üzerinde yatay/dikey Sobel, yatay/dikey Prewitt, kaydır çıkart, alçak geçiren filtre, yüksek geçiren filtre ve Gauss filtre işlemleri kullanıcı tarafından ayarlanan parametre ile kolaylık gerçeklenebilmektedir. IP çekirdek platform bağımsız olarak tasarlanmıştır ve tüm FPGA üreticileri tarafından geliştirilen yazılımlarda sentezlenebilmektedir. IP çekirdeğine ait sentez sonuçları Xilinx firmasının Artix 7 100T FPGA’sı referans alınarak verilmiştir. Sentez sonuçları çalışma kapsamında geliştirilen iki boyutlu konvolüsyon IP çekirdeğinin düşük donanım maliyeti ile FPGA tabanlı gerçeklendiğini göstermiştir.

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Cite This Article

ÇAVUŞLU, M. A. (2021). FPGA Based Implementation of 2D Convolution Processing as a Low-Cost IP Core. Dicle Üniversitesi Fen Bilimleri Enstitüsü Dergisi, Cilt: 10 - Sayı: 2, 235–245. https://ajindex.com/articles/386877

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