FPGA implementation of a low-power and area-efficient state-table-based compression algorithm for DSLR cameras

Abstract

Small image acquisition devices like digital single lens reflex (DSLR) cameras most commonly use JointPhotographic Expects Group (JPEG) coding standard for lossy compression. Although JPEG is a simple codingstandard, its compression efficiency is very low as compared to any typical state-of-the-art image coding standardslike set partitioning in hierarchical trees (SPIHT). In this paper, a novel state-table-based SPIHT (STS) algorithm andits field programmable gate array (FPGA) implementation is proposed. The STS uses two small state-tables and twoextremely small lists. The STS not only provides better compression efficiency than the state-of-the-art JPEG 2000at high bit rates but also requires very small memory to hold the state-tables and lists in comparison to SPIHT. Onaverage STS requires 0.86% of the memory needed by SPIHT when evaluated for image sizes ranging from 4 Mpixels to40 Mpixels. The implementation results show that STS consumes very less FPGA area in comparison to SPIHT-basedarchitectures. The dynamic power dissipation of STS is also less than that of JPEG-like compression standards. Thismakes our proposed algorithm a better candidate for compression in low-power, low-memory digital image acquisitiondevices