Design of a spurious-free RF frequency synthesizer for fast-settling receivers

Abstract

A tunable reference clock frequency topology is presented as a spur reduction application for frequencysynthesizers of fast frequency hopping spread spectrum systems. The method was verified by measurements on adesigned hardware operating at L-band frequencies. This spur reduction method is based on optimizing the referenceclock frequency of synthesizers to mitigate spurs. By using the spur reduction method, the power of spurious signalswas reduced up to 57 dB. The performance of the spur reduction method was also analyzed at different loop-filterconfigurations. Smaller lock time was obtained by enlarging the bandwidth of the loop filter up to 150 kHz. Therequired power response of the spurious signals specified in telecommunication standards was achieved even though theloop filter bandwidth was enlarged.Key words: Fast-frequency hopping spread spectrum, spurious-free, integer-boundary spur, synthesizer, fractionalphase-lock loop, L-band, receiver, transmitter, RF phase-lock loop, spur mitigation