A brief outline of the two level CTL realization and its comparison with the new implementation are given as far as their transistor count, programmability and total delay are concerned.
📌 3 Maddede Bu Makale
🎯
Amaç & Hipotez:The implementation of a perceptron that can classify data separable by two parallel hyper-planes or equivalently of a Single-Level TL-XOR gate is proposed using 10 MOS transistors and 2 capacitors.
📊
Temel Bulgular & Veri:The functional subblock decomposition of the Perceptron with two separating hyper-planes, its CMOS implementation explaining the operation of each sub-block and simulation results, obtained using the SpectreS simulator and AMS 0.8 $mu m$ CMOS double-poly double-metal technology parameters are presented.
💡
Sonuç & Katkı:A brief outline of the two level CTL realization and its comparison with the new implementation are given as far as their transistor count, programmability and total delay are concerned.
🔬Tür:Araştırma Makalesi
📍Kapsam:Genişletilmiş Akademik Örneklem
⚙️Değişkenler:Alan Parametreleri
Abstract
The implementation of a perceptron that can classify data separable by two parallel hyper-planes or equivalently of a Single-Level TL-XOR gate is proposed using 10 MOS transistors and 2 capacitors. The functional subblock decomposition of the Perceptron with two separating hyper-planes, its CMOS implementation explaining the operation of each sub-block and simulation results, obtained using the SpectreS simulator and AMS 0.8 $mu m$ CMOS double-poly double-metal technology parameters are presented. A brief outline of the two level CTL realization and its comparison with the new implementation are given as far as their transistor count, programmability and total delay are concerned.
🔖
Bu Makaleye Atıf Yap
GÖKNAR, İ. C., ARAS, S., AKSIN, D. Y. (2022). Realization and extensions of user programmable, single-level, double-threshold generalized perceptron. Istanbul University Journal of Electrical and Electronics Engineering, Cilt: 1 - Sayı: 1, 123–129. https://ajindex.com/articles/543974
Rosenblatt, F., "The perceptron: A probabilistic model for information storage and organisation in the brain." Psychological Review 65, 386-408, 1958
Haykin, S., Neural Networks. A Comprehensive Foundation, New York: Macmillan College Publishing, 1994
Aksın,D.Y., A Programmable CMOS Analog Vector Quantizer Chip. MSc. Thesis, İTÜ, Aug 1999
Özdemir, H. et al, "Capacitive threshold logic gate," IEEE J. of Solid State Circuits 31, 8, 1141-1150, Aug. 1996
Leblebici, Y. et al, "Compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gates," IEEE Journal of Solid-State Circuits 31, 8, 1177-1183, Aug 1996.