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Dergiler / Electronic Letters on Science and Engineering / 2021 / Volume: 17 Issue: 2

An Implementation of Linear Regression using IP-Core and FPGA-based Microcomputer Architecture

Abdelkader Lazzem(SAKARYA UYGULAMALI BİLİMLER ÜNİVERSİTESİ)0000-0003-0136-356X
Halit Öztekin(SAKARYA UYGULAMALI BİLİMLER ÜNİVERSİTESİ)0000-0001-8598-4763
Souad Cheurfı(SAKARYA UYGULAMALI BİLİMLER ÜNİVERSİTESİ)0000-0003-4053-3971
Sayfa
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Yayın Tarihi
2021-12-31
DOI
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⚡ TL;DR(1 Cümlede Hızlı Çıkarım)

After implementing both ways we have calculated the mean square error MSE between them and found the result is 7.8×10^(-4).

📌 3 Maddede Bu Makale

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Amaç & Hipotez:To generate more accurate results, machine learning approaches, particularly those based on neural networks, require the usage of accurate real values.
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Temel Bulgular & Veri:In this paper, to demonstrate the FPGA-based half-precision floating-point (FPU-16) implementation .Two different ways for implementing linear regression are proposed. the first method is by using the assembler of BZK.SAU.FPGA-based microcomputer architecture.
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Sonuç & Katkı:After implementing both ways we have calculated the mean square error MSE between them and found the result is 7.8×10^(-4).
🔬Tür:Modelleme & Sayısal Simülasyon
📍Kapsam:Genişletilmiş Akademik Örneklem
⚙️Değişkenler:Artificial Neural Network (AAN) · Machine Learning (ML) · Half-precision Floating-point

Abstract

To generate more accurate results, machine learning approaches, particularly those based on neural networks, require the usage of accurate real values. Linear regression is a machine learning technique that is commonly used to identify the linear function that best fits a set of data. Due to current trends in systems need and the availability of Field-Programmable Gate Array (FPGA), floating-point implementations are becoming more widespread, and engineers are increasingly using FPGAs as a platform for floating-point implementations. In this paper, to demonstrate the FPGA-based half-precision floating-point (FPU-16) implementation .Two different ways for implementing linear regression are proposed. the first method is by using the assembler of BZK.SAU.FPGA-based microcomputer architecture. The second method is by using IP-Core of Xilinx simulated and tested using Vivado Design Suite software. After implementing both ways we have calculated the mean square error MSE between them and found the result is 7.8×10^(-4).

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Bu Makaleye Atıf Yap

Lazzem, A., Öztekin, H., Cheurfı, S. (2021). An Implementation of Linear Regression using IP-Core and FPGA-based Microcomputer Architecture. Electronic Letters on Science and Engineering, Volume: 17 Issue: 2. https://ajindex.com/articles/1180977

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Kaynakça (11)

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