A power and area efficient approximate carry skip adder for error resilient applications

Abstract

The compute-intensive multimedia applications on portable devices require power and area efficient arithmetic units. The adder is a prime building block of these arithmetic units and limits the overall performance. Therefore,this paper analyzes the logic operations of the state-of-the-art adders and presents a novel low complexity adder segmentwith new carry prediction logic by removing the redundant logic and sharing the common operations. Further, a newpower and area efficient approximate carry skip (PAEA-CSK) adder is proposed using the novel adder segment. The effectiveness of the proposed PAEA-CSK adder is evaluated and compared over the existing adders by implementing themin VHDL and synthesizing using the Synopsys Design Compiler with the 65nm TSMC CMOS Library. The synthesisresult shows that the proposed PAEA-CSK adder requires 27.28% and 18.03% less area and power, respectively, overthe existing carry skip-based approximate adder with the same accuracy. Further, the Sobel edge detector (SED) embedded with the proposed adder improves PSNR by a minimum of 16.94 dB over the SED embedded with a nonzeroingbit-truncation adder.