A novel efficient TSV built-in test for stacked 3D ICs

Abstract

A through-silicon via (TSV) is established as the main enabler for a three-dimensional integrated circuit(3D IC) that increases system density and compactness. The exponential increase in TSV density led to TSV-inducedcatastrophic and parametric faults. We propose an original architecture that detects errors caused by TSV manufacturingdefects. The proposed design for testability is a built-in technique that detects errors in an early manufacturing stageand is hence very economically attractive. The proposal is capable of testing each and every TSV in the network. Thetechnique achieves high fault coverage and high observability.