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Journals / Istanbul University Journal of Electrical and Electronics Engineering / 2014 / Cilt: 14 - Sayı: 2

FPGA BASED HARDWARE IMPLEMENTATION OF WTHD MINIMISATION IN ASYMMETRIC MULTILEVEL INVERTER USING BIOGEOGRAPHICAL BASED OPTIMISATION

R KAVİTHA
Rani THOTTUNGAL
Pages
1799–1807
Publication Date
2022-10-18
DOI
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AI Summary & Key Takeaways

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⚡ TL;DR(Too Long; Didn't Read)

The experimental waveforms were analysed for THD and lower order harmonics using fluke power analyser and comparison of WTHD with SHE-PWM and OMTHD are presented .The results indicates that in a 13 level inverter the WTHD based optimisation yields reduced THD of 5.35% in simulation and 5.9% experimentally.It also eliminates all the specified 5th ,7th ,11th ,13th and 17th lower order harmonics

📌 3 Key Takeaways

🎯
Objective & Hypothesis:Harmonic Elimination and THD Minimisation in asymmetric cascaded multilevel inverter involves complex nonlinear non convex trigonometric transcendental equations which has several solutions.Among the various topologies of cascaded multilevel inverter asymmetric cascaded multilevel inverter has the advantage of reduced switch count when compared to traditional symmetric multilevel inverter topology.
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Key Findings & Data:In this paper FPGA based hardware implementation is carried for a 13 level inverter by using offline computation of switching angle with weighted total harmonic distortion (WTHD) as the objective function.
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Conclusion & Impact:The experimental waveforms were analysed for THD and lower order harmonics using fluke power analyser and comparison of WTHD with SHE-PWM and OMTHD are presented .The results indicates that in a 13 level inverter the WTHD based optimisation yields reduced THD of 5.35% in simulation and 5.9% experimentally.It also eliminates all the specified 5th ,7th ,11th ,13th and 17th lower order harmonics
🔬Design:Research Article
📍Scope:Comprehensive Sample
⚙️Variables:Domain Parameters

Abstract

Harmonic Elimination and THD Minimisation in asymmetric cascaded multilevel inverter involves complex nonlinear non convex trigonometric transcendental equations which has several solutions.Among the various topologies of cascaded multilevel inverter asymmetric cascaded multilevel inverter has the advantage of reduced switch count when compared to traditional symmetric multilevel inverter topology. In this paper FPGA based hardware implementation is carried for a 13 level inverter by using offline computation of switching angle with weighted total harmonic distortion (WTHD) as the objective function. WTHD optimisation offers the blend of eliminating the specific lower order harmonics as in SHE-PWM and minimisation of THD as in OMTHD. The simulation and experimental results were presented for 7 level symmetric and 13 level asymmetric inverter. The experimental waveforms were analysed for THD and lower order harmonics using fluke power analyser and comparison of WTHD with SHE-PWM and OMTHD are presented .The results indicates that in a 13 level inverter the WTHD based optimisation yields reduced THD of 5.35% in simulation and 5.9% experimentally.It also eliminates all the specified 5th ,7th ,11th ,13th and 17th lower order harmonics

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Cite This Article

KAVİTHA, R., THOTTUNGAL, R. (2022). FPGA BASED HARDWARE IMPLEMENTATION OF WTHD MINIMISATION IN ASYMMETRIC MULTILEVEL INVERTER USING BIOGEOGRAPHICAL BASED OPTIMISATION. Istanbul University Journal of Electrical and Electronics Engineering, Cilt: 14 - Sayı: 2, 1799–1807. https://ajindex.com/articles/543658

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