✨
AI Summary & Key Takeaways
AI Insight⚡ TL;DR(Too Long; Didn't Read)
The core design consumes 6.01µW power and overall design consumes 17.06µW.
📌 3 Key Takeaways
🎯
Objective & Hypothesis:In this work, low-power dynamic comparator is presented with auto-zeroing technique for successive approximation register (SAR) analogue-to-digital converter (ADC).
📊
Key Findings & Data:The comparator designed with DTMOS technique operates in subthreshold region.
💡
Conclusion & Impact:The core design consumes 6.01µW power and overall design consumes 17.06µW.
🔬Design:Research Article
📍Scope:Comprehensive Sample
⚙️Variables:SAR ADC · Comparator · CMOS analog integrated circuits
Abstract
In this work, low-power dynamic comparator is presented with auto-zeroing technique for successive approximation register (SAR) analogue-to-digital converter (ADC). The comparator designed with DTMOS technique operates in subthreshold region. The designed circuit consumes low power with high gain. The dynamic range of the comparator is increased with a new biasing technique for DTMOS transistors. The core design consumes 6.01µW power and overall design consumes 17.06µW. The design is realized with two different supply voltage with 600mV (core design) and 1.8V (biasing circuit). The comparator has been simulated with 0.18µm TSMC process in Cadence environment.
🔖
Cite This Article
ALAYBEYOGLU, E. (2020). LOW-POWER DYNAMIC COMPARATOR WITH HIGH PRECISION FOR SAR ADC. Turkish Journal of Engineering, Cilt: 4 - Sayı: 2, 85–91. https://ajindex.com/articles/370925