SavedAdd your journal

Journals / International Journal of Information Security Science / 2026 / Volume: 15 Issue: 3

A Secure Logic Locking Integration Technique for AES Algorithm

Priyadharshini M(Sri Ramakrishna Engineering College)0000-0001-6378-7478
Saravanan P(PSG College of Technology)0000-0003-0785-807X
Pages
—
Publication Date
2026-09-30
🏛️Bibliographic metadata and full text access for this article are provided via DergiPark.
DergiPark Record ↗
✨

AI Summary & Key Takeaways

AI Insight
⚡ TL;DR(Too Long; Didn't Read)

Experimental results demonstrate approximately 50\% output corruption under incorrect keys and incorrect key convergence during SAT attack attempts across multiple key sizes.

📌 3 Key Takeaways

🎯
Objective & Hypothesis:The globalization of semiconductor manufacturing has increased vulnerabilities such as hardware Trojan insertion, overbuilding, reverse engineering, and intellectual property piracy.
📊
Key Findings & Data:Logic locking has emerged as an effective countermeasure to protect integrated circuits using secret key activation.
💡
Conclusion & Impact:Experimental results demonstrate approximately 50\% output corruption under incorrect keys and incorrect key convergence during SAT attack attempts across multiple key sizes.
🔬Design:Research Article
📍Scope:Comprehensive Sample
⚙️Variables:logic locking · SAT · Hardware Trojans

Abstract

The globalization of semiconductor manufacturing has increased vulnerabilities such as hardware Trojan insertion, overbuilding, reverse engineering, and intellectual property piracy. Logic locking has emerged as an effective countermeasure to protect integrated circuits using secret key activation. The Advanced Encryption Standard (AES) is widely deployed in Internet of Things (IoT) systems and therefore requires robust hardware-level protection. This work presents an architecture-level integration of Random Logic Locking and an Anti-SAT block within an AES encryption core implemented on an Artix-7 FPGA. Unlike prior studies that primarily evaluate Anti-SAT on benchmark circuits, the proposed approach embeds the locking framework directly into a complete cryptographic datapath and analyzes both hardware overhead and security characteristics. The design is evaluated in terms of area, power, throughput, Hamming distance corruptibility, and Satisfiability Checking(SAT) attack resilience. Experimental results demonstrate approximately 50\% output corruption under incorrect keys and incorrect key convergence during SAT attack attempts across multiple key sizes. The results indicate that the proposed integration enhances SAT attack resistance while maintaining acceptable hardware overhead, making it suitable for secure IoT hardware deployments.

🔖

Cite This Article

M, P., P, S. (2026). A Secure Logic Locking Integration Technique for AES Algorithm. International Journal of Information Security Science, Volume: 15 Issue: 3. https://doi.org/10.55859/ijiss.1795996

📄 Full Text PDF Viewer

📄

PDF görüntüleyici hazırlanıyor...

References (54)

  1. M. Yasin and O. Sinanoglu, “Evolution of logic locking,” in International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2017, pp. 1–6.
  2. J. A. Roy, F. Koushanfar, and I. L. Markov, “Epic: Ending piracy of integrated circuits,” in Proceedings of the Conference on Design, Automation & Test in Europe, 2008, pp. 1069–1074.
  3. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, “Logic encryption: A fault analysis perspective,” in Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2012, pp. 953–958.
  4. J. Rajendran, H. Zhang et al., “Fault analysis-based logic encryption,” IEEE Transactions on Computers, vol. 64, no. 2, pp. 410–424, 2013.
  5. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, “Security analysis of logic obfuscation,” in Proceedings of the 49th Annual Design Automation Conference, 2012, pp. 83–89.
  6. K. Xiao, D. Forte, and M. Tehranipoor, “A novel built-in self-authentication technique to prevent inserting hardware trojans,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 12, pp. 1778–1791, 2014.
  7. S. Dupuis, P.-S. Papa-Sidi Ba, G. Di Natale, M.-L. Flottes, and B. Rouzeyre, “A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans,” in International On-Line Testing Symposium (IOLTS). IEEE, 2014, pp. 49–54.
  8. V. S. Rathor, B. Garg, and G. K. Sharma, “A novel low complexity logic encryption technique for design-for-trust,” IEEE Transactions on Emerging Topics in Computing, vol. 8, no. 3, pp. 688–699, 2018.
  9. S. Amir, B. Shakya, D. Forte, M. Tehranipoor, and S. Bhunia, “Comparative analysis of hardware obfuscation for IP protection,” in Proceedings of the Great Lakes Symposium on VLSI, 2017, pp. 363–368.
  10. A. Chakraborty, N. Gummidipoondi Jayasankaran, Y. Liu et al., “Keynote: A disquisition on logic locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 10, pp. 1952–1972, 2019.
  11. T. Hoque, R. S. Chakraborty, and S. Bhunia, “Hardware obfuscation and logic locking: A tutorial introduction,” IEEE Design & Test, vol. 37, no. 3, pp. 59–77, 2020.
  12. H. M. Kamali, K. Z. Azar, F. Farahmandi, and M. Tehranipoor, “Advances in logic locking: Past, present, and prospects,” Cryptology ePrint Archive, 2022.
  13. P. Subramanyan, S. Ray, and S. Malik, “Evaluating the security of logic encryption algorithms,” in International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2015, pp. 137–143.
  14. Y.-W. Lee and N. A. Touba, “Improving logic obfuscation via logic cone analysis,” in Latin-American Test Symposium (LATS). IEEE, 2015, pp. 1–6.
  15. K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y. Jin, “Appsat: Approximately deobfuscating integrated circuits,” in International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2017, pp. 95–100.
  16. Y. Shen and H. Zhou, “Double dip: Re-evaluating security of logic encryption algorithms,” in Proceedings of the Great Lakes Symposium on VLSI, 2017, pp. 179–184.
  17. M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran, “Security analysis of anti-sat,” in Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2017, pp. 342–347.
  18. M. Yasin, B. Mazumdar, S. S. Ali, O. Sinanoglu et al., “Removal attacks on logic locking and camouflaging techniques,” in IEEE Transactions on Emerging Topics in Computing, vol. 8, no. 2, pp. 517–532, 2017.
  19. X. Xu, B. Shakya, M. M. Tehranipoor, and D. Forte, “Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks,” in Cryptographic Hardware and Embedded Systems (CHES). Springer International Publishing, 2017, pp. 189–210.
  20. P. Chakraborty, J. Cruz, and S. Bhunia, “Sail: Machine learning guided structural analysis attack on hardware obfuscation,” in Asian Hardware Oriented Security and Trust Symposium (AsianHOST). IEEE, 2018, pp. 56–61.
  21. P. Kocher, J. Jaffe, and B. Jun, “Differential power analysis,” in Advances in Cryptology–CRYPTO’99. Springer Berlin Heidelberg, 1999, pp. 388–397.
  22. M. Yasin, B. Mazumdar, S. S. Ali, and O. Sinanoglu, “Security analysis of logic encryption against the most effective side-channel attack: DPA,” in International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). IEEE, 2015, pp. 97–102.
  23. A. Baumgarten, A. Tyagi, and J. Zambreno, “Preventing IC piracy using reconfigurable logic barriers,” IEEE Design & Test of Computers, vol. 27, no. 1, pp. 66–75, 2010.
  24. J. B. Wendt and M. Potkonjak, “Hardware obfuscation using PUF-based logic,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2014, pp. 270–271.
  25. S. M. Plaza and I. L. Markov, “Solving the third-shift problem in IC piracy with test-aware logic locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 6, pp. 961–971, 2015.
  26. S. Khaleghi, K. D. Zhao, and W. Rao, “IC piracy prevention via design withholding and entanglement,” in Asia and South Pacific Design Automation Conference. IEEE, 2015, pp. 821–826.
  27. B. Liu and B. Wang, “Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,” in Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2014, pp. 1–6.
  28. G. Kolhe, H. M. Kamali, M. Naicker et al., “Security and complexity analysis of lut-based obfuscation: From blueprint to reality,” in International Conference on Computer-Aided Design (ICCAD). IEEE, 2019, pp. 1–8.
  29. R. S. Chakraborty and S. Bhunia, “Harpoon: An obfuscation-based soc design methodology for hardware protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493–1502, 2009.
  30. Y. Lao and K. K. Parhi, “Obfuscating DSP circuits via high-level transformations,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 819–830, 2014.
  31. M. I. Shiny and M. N. Devi, “Trustworthy scan design and testability using obfuscation and logic locking scheme for wireless network application,” Mobile Networks and Applications, vol. 27, no. 3, pp. 1000–1018, 2022.
  32. M. Yasin, B. Mazumdar, J. J. Rajendran, and O. Sinanoglu, “Sarlock: Sat attack resistant logic locking,” in International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2016, pp. 236–241.
  33. Y. Xie and A. Srivastava, “Anti-sat: Mitigating sat attack on logic locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 2, pp. 199–207, 2018.
  34. M. Yasin, A. Sengupta, B. Carrion Schafer, Y. Makris, O. Sinanoglu, and J. Rajendran, “What to lock? functional and parametric locking,” in Proceedings of the Great Lakes Symposium on VLSI, 2017, pp. 351–356.
  35. M. Yasin, A. Sengupta, M. T. Nabeel, M. Ashraf, J. Rajendran, and O. Sinanoglu, “Provably-secure logic locking: From theory to practice,” in ACM SIGSAC Conference on Computer and Communications Security, 2017, pp. 1601–1618.
  36. K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y. Jin, “Cyclic obfuscation for creating sat-unresolvable circuits,” in Proceedings of the Great Lakes Symposium on VLSI, 2017, pp. 173–178.
  37. M. S. Rahman, A. Nahiyan, S. Amir et al., “Dynamically obfuscated scan chain to resist oracle-guided attacks on logic locked design,” Cryptology ePrint Archive, 2019.
  38. V. S. Rathor, B. Garg, and G. K. Sharma, “New lightweight anti-sat block design and obfuscation technique to thwart removal attack,” Integration, vol. 75, pp. 178–188, 2020.
  39. Y. Liu, M. Zuzak, Y. Xie, A. Chakraborty, and A. Srivastava, “Strong anti-sat: Secure and effective logic locking,” in International Symposium on Quality Electronic Design (ISQED). IEEE, 2020, pp. 199–205.
  40. J. Zhou and X. Zhang, “Generalized sat-attack-resistant logic locking,” IEEE Transactions on Information Forensics and Security, vol. 16, pp. 2581–2592, 2021.
  41. N. Kajtez, Y. Zhang, and B. Halak, “Lockit: A logic locking automation software,” Electronics, vol. 10, no. 22, p. 2817, 2021.
  42. M. Yue and S. Tehranipoor, “A novel probability-based logic-locking technique: Problock,” Sensors, vol. 21, no. 23, p. 8126, 2021.
  43. Z. Mirmohammadi and S. E. Borujeni, “A new optimal method for the secure design of combinational circuits against hardware trojans using interference logic locking,” Electronics, vol. 12, no. 5, p. 1107, 2023.
  44. W. Wang, L. Zhao, and S. Cai, “Replacement-based key-controlled circuits: A new lightweight logic-locking technique to prevent the SAT attack and its variants,” Applied Sciences, vol. 16, no. 2, p. 925, 2026.
  45. D. Liao, D. Lei, X. Liu, X. Yang, L. Zhang, and Y. Liu, “Dcll: Depth-coupling based approach on logic locking,” IEICE Electronics Express, vol. 23, no. 2, pp. 20 250 229–20 250 229, 2026.
  46. V. S. Rathor, M. Singh, K. S. Sahoo, and S. P. Mohanty, “Gatelock: Input-dependent key-based locked gates for sat resistant logic locking,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 2, pp. 361–371, 2023.
  47. S. Kamatchi, A. S. Priya, E. L. Prasad, M. T. Rani, V. S. Pranav, J. Bahadur, and D.-W. Kang, “Design and implementation of an enhanced anti-sat framework for robust protection against sat-based attacks on logic-locked circuits,” Results in Engineering, p. 105928, 2025.
  48. D. Upadhyaya, M. Gay, and I. Polian, “Leda: Locking enabled differential analysis of cryptographic circuits,” in International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2023, pp. 249–259.
  49. K. Taka, K. Sakamoto, R. Ito, R. Shiba, S. Utsumi, and T. Isobe, “Divide-and-conquer SAT for exploring optimal differential and linear characteristics and its applications,” IACR Transactions on Symmetric Cryptology, vol. 2025, no. 3, pp. 516–576, 2025.
  50. S. Chhabra and K. Lata, “Design and analysis of logic encryption-based 128-bit AES algorithm: A case study,” in India Council International Conference (INDICON). IEEE, 2018, pp. 1–6.
  51. S. Chhabra and K. Lata, “Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications,” Concurrency and Computation: Practice and Experience, vol. 34, no. 21, p. e7058, 2022.
  52. S. Chhabra and K. Lata, “Towards the enhancement of AES IP security using hardware obfuscation technique: A practical approach for secure data transmission in IoT,” Security and Privacy, vol. 5, no. 4, p. e233, 2022.
  53. X. Zhang and K. K. Parhi, “High-speed VLSI architectures for the AES algorithm,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 957–967, 2004.
  54. S. Amir, B. Shakya, X. Xu et al., “Development and evaluation of hardware obfuscation benchmarks,” Journal of Hardware and Systems Security, vol. 2, pp. 142–161, 2018.