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Journals / Electrica / 2017 / Cilt: 17 Sayı: 1

A NOVEL REVERSIBLE FAULT TOLERANT MICROPROCESSOR DESIGN IN AMS 0.35UM PROCESS

M. Hüsrev CILASUN
Mustafa ALTUN
Journal
Electrica
Pages
3169–3178
Publication Date
2017-03-27
DOI
—
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AI Summary & Key Takeaways

AI Insight
⚡ TL;DR(Too Long; Didn't Read)

The design is simulated in ams 0.35um process and a layout is obtained for tapeout.

📌 3 Key Takeaways

🎯
Objective & Hypothesis:In this study, reversible circuits are revisited to achieve extreme soft-defect awareness in classical CMOS circuits.
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Key Findings & Data:A reversible 8-bit full adder is designed in 12-bit block code domain.
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Conclusion & Impact:The design is simulated in ams 0.35um process and a layout is obtained for tapeout.
🔬Design:Review & Systematic Survey
📍Scope:Comprehensive Sample
⚙️Variables:Reversible Computing · Fault Tolerance · Microprocessor

Abstract

In this study, reversible circuits are revisited to achieve extreme soft-defect awareness in classical CMOS circuits. Defect models in the literature are reviewed and defect scattering is analyzed. A reversible 8-bit full adder is designed in 12-bit block code domain. As a proof of concept, a pair of reversible ALUs are embedded into a microprocessor with block-code encoded data-path. The design is simulated in ams 0.35um process and a layout is obtained for tapeout.

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Cite This Article

CILASUN, M. H., ALTUN, M. (2017). A NOVEL REVERSIBLE FAULT TOLERANT MICROPROCESSOR DESIGN IN AMS 0.35UM PROCESS. Electrica, Cilt: 17 Sayı: 1, 3169–3178. https://ajindex.com/articles/1017409

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