Design and Implementation of Area and Power Efficient Reconfigurable FIR Filter with Low Complexity Coefficients

Abstract

This paper presents the design and implementation of area and power efficient reconfigurablefinite impulse response (FIR) filter. We present a method for designing a reconfigurable filterwith low binary complexity coefficients (LBCC) and thus to optimize the filter while satisfyingthe design specifications. The total number of non zero binary bits is taken as a measure of thebinary complexity (BC) of a coefficient. We propose two implementation architectures namelysigned-magnitude architecture (SMA) and signed-decimal architecture (SDA) which are basedon 3-bit binary common sub expression elimination (BCSE) algorithm and vertical horizontalBCSE (VHBCSE) algorithm respectively. SMA and SDA reduce the redundant computations ofthe coefficient multiplications in the filter. The proposed filters are synthesized on tsmc 65nmCMOS technology. The synthesis results show that the proposed filters are area and powerefficient when compared with the existing ones.